About the position

This position is not currently open; however, we are posting for future positions that range from Junior to Senior levels for our San Jose Design Center. Overview of Role We are seeking a highly talented and motivated Senior Memory Design Engineer with deep expertise in SRAM and memory compiler development to join our innovative team. As a Senior Memory Design Engineer, you will leverage TSMC’s leading-edge process technologies and comprehensive design enablement solutions to drive groundbreaking innovations for the global semiconductor industry. Join us in the San Jose Design Office and be part of the team that pushes the boundaries of what’s possible in advanced memory design. You will report to the Director of Memory Design Team in San Jose, California. We operate on a hybrid work schedule with 4 days in the office, fostering a collaborative and dynamic environment.

Responsibilities

• Drive the design, characterization, and verification methodology for advanced Memory IP at the compiler level, directly impacting SoC designs in customer products.
• Implement custom digital and analog circuits for advanced SRAM/DRAM/Non-Volatile memory designs, collaborating closely with logic and architecture teams to define comprehensive specifications.
• Lead and execute memory compiler development, including timing/power characterization, netlist/layout tiling, and IR/EM flow analysis.
• Oversee and provide technical guidance for layout optimization, compiler coding, and the interpretation of silicon testing results and debug activities.
• Conduct silicon debug and chip failure analysis for various customers, contributing to continuous improvement and next-generation design.
• Perform PPPA (Power, Performance, Area) optimization to meet stringent customer requirements across various technology nodes.
• Develop and implement design schemes for low power (LS/DS/SD), dual-rail, BIST, and foundry-based Write-Assist and Read-Assist circuitry.
• Collaborate strategically with cross-functional teams and Headquarters in Hsinchu, Taiwan, ensuring functional products are delivered efficiently.
• Act as a hands-on technical contributor for all compiler-related work, encompassing circuit design, automation, and verification.

Requirements

• Master’s degree in Electrical/Computer Engineering with 5+ years of related work experience; or a Bachelor’s degree in Electrical/Computer Engineering with 7+ years of related work experience.
• Demonstrated expertise in Memory IP design, characterization, and verification methodologies at the compiler level.
• In-depth knowledge and hands-on experience with advanced SRAM compiler development, utilizing Cadence and Synopsys circuit design environments.
• Proven experience in advanced technology node circuit design (TSMC N10 or below, including TS7, GF22, Intel10, etc.) and layout.
• Expertise in scripting languages such as Perl/Shell/TCL/Python for design automation, simulation, and QA flow.
• Strong understanding of bitcell analysis, critical margin validation, and simulation setup.
• Experience in designing low-power techniques (LS/DS/SD), dual-rail, BIST, and foundry-based Write-Assist/Read-Assist circuitry.

Nice-to-haves

• Ph.D. in Electrical/Computer Engineering with a focus on memory circuit design.
• Exposure to TSMC N5 and below technology.
• Experience leading or coordinating design projects, including collaboration with layout and QA engineers.
• Advanced static timing analysis and sign-off capabilities.
• Track record in multi-million gate design production tapeouts.
• Strong interpersonal skills, excellent teamwork attitude, and the ability to work effectively under pressure in a fast-paced, collaborative environment.
• Knowledge of layout optimization techniques to improve yield, reduce RC loading, and optimize design size.
• Published research or patents related to memory circuit design.